I use CUAV X7 pro have tried to add ADIS16470 , but 16bit spi not use, spi6 dma not use yet, unused DMA result in high cpu utilization, someone has same problem, now i saved spi6 dma problems .
I have faced the same problem and could not figure out.
Now i use 2 8bit can use ,but not use DMA
Could you share the code if it possible?
modify Firmware/platforms/nuttx/NuttX/nuttx/arch/arm/src/stm32h7/stm32_spi.c
static void spi_setbits(FAR struct spi_dev_s *dev, int nbits)
{
FAR struct stm32_spidev_s *priv = (FAR struct stm32_spidev_s *)dev;
uint32_t setbits = 0;
uint32_t clrbits = 0;
int savbits = nbits;
//spiwarn(“nbits=%d\n”, nbits);
/* Has the number of bits changed? */
if (nbits != priv->nbits)
{
/* Yes… Set CFG1 appropriately */
/* Set the number of bits (valid range 4-32) */
if (nbits < 4 || nbits > 32)
{
return;
}
clrbits = SPI_CFG1_DSIZE_MASK;
setbits = SPI_CFG1_DSIZE_VAL(8);
/* REVISIT: FIFO threshold level */
/* If nbits is <=8, then we are in byte mode and FRXTH shall be set
* (else, transaction will not complete).
*/
if (nbits < 9)
{
setbits |= SPI_CFG1_FTHLV_1DATA; /* RX FIFO Threshold = 1 byte */
}
else
{
setbits |= SPI_CFG1_FTHLV_1DATA; /* RX FIFO Threshold = 2 byte */
}
spi_enable(priv, false);
spi_modifyreg(priv, STM32_SPI_CFG1_OFFSET, clrbits, setbits);
spi_enable(priv, true);
uint32_t regval = spi_getreg(priv, STM32_SPI_CFG1_OFFSET);
spiwarn("cfg:%x %x\n", regval, spi_getreg(priv, STM32_SPI_SR_OFFSET));
/* Save the selection so the subsequence re-configurations will be
* faster
*/
priv->nbits = savbits; /* nbits has been clobbered... save the signed value */
}
}
static uint32_t spi_send(FAR struct spi_dev_s *dev, uint32_t wd)
{
FAR struct stm32_spidev_s *priv = (FAR struct stm32_spidev_s *)dev;
uint32_t regval = 0;
uint32_t ret = 0;
DEBUGASSERT(priv && priv->spibase);
/* Clear suspend flag */
spi_modifyreg(priv, STM32_SPI_IFCR_OFFSET, 0, SPI_IFCR_SUSPC);
/* Master transfer start */
if (priv->config != SIMPLEX_RX)
{
spi_modifyreg(priv, STM32_SPI_CR1_OFFSET, 0, SPI_CR1_CSTART);
}
/* According to the number of bits, access data register as word or byte
- This is absolutely required because of packing. With nbits <=8 bit
- frames, two bytes are received by a 16-bit read of the data register!
*/
if (priv->nbits > 8)
{
// spi_writeword(priv, wd);
// ret = spi_readword(priv);
uint8_t *buf = (uint8_t *)&wd;
spi_writebyte(priv, buf[1]);
spi_writebyte(priv, buf[0]);
ret = (uint32_t)spi_readbyte(priv);
ret = ret << 8 | (uint32_t)spi_readbyte(priv);
}
else
{
spi_writebyte(priv, (uint8_t)(wd & 0xff));
ret = (uint32_t)spi_readbyte(priv);
}
/* Check and clear any error flags (Reading from the SR clears the error
- flags).
*/
regval = spi_getreg(priv, STM32_SPI_SR_OFFSET);
/* Suspend */
spi_modifyreg(priv, STM32_SPI_CR1_OFFSET, 0, SPI_CR1_CSUSP);
while ((spi_getreg(priv, STM32_SPI_SR_OFFSET) & SPI_SR_SUSP) == 0);
/* Dump some info */
if (priv->nbits > 8)
{
// spiwarn(“CR1: 0x%08x CFG1: 0x%08x CFG2: 0x%08x\n”,
// spi_getreg(priv, STM32_SPI_CR1_OFFSET),
// spi_getreg(priv, STM32_SPI_CFG1_OFFSET),
// spi_getreg(priv, STM32_SPI_CFG2_OFFSET));
// spiwarn(“IER: 0x%08x SR: 0x%08x I2SCFGR: 0x%08x\n”,
// spi_getreg(priv, STM32_SPI_IER_OFFSET),
// spi_getreg(priv, STM32_SPI_SR_OFFSET),
// spi_getreg(priv, STM32_SPI_I2SCFGR_OFFSET));
//spiwarn(“Sent%d: %04x Return: %04x Status: %02x\n”,priv->nbits, wd, ret, regval);
}
else
{
//spiwarn(“Sent%d: %02x Return: %02x Status: %02x\n”,priv->nbits, wd, ret, regval);
}
UNUSED(regval);
return ret;
}