Hardware/Pixhawk Dev Call: Sept 10, 2019

Note taking for the Opensource PX4 Meeting zoom meeting call.

XL and Medium version
Medium - 80 or 100 pin connector with 40 pin connector. (spec elsewhere)

Initially Phy should go on FMU-M then moved to carrier board as it makes integrators job easier.

  • con - Ethernet is a future item, so then

If we have to grow the baord, would we be better using larger package for the processor and larger pinout? (208 package?)

Should we look at doing H7 and fitting that in whatever footprint, then implementing the F7

Package - have not yet determined if it makes sense yet. Features on larger package in really just GPIO.
Deadlocked on pin in some instanced - Lose CAN 2 on F7 , Lose SPI for example.
High speed OTG - uses 12 more pins. But lose more things - so maybe no advantage.

Dougan to comment on if increase in size makes routing better.

Some emissions issues - 50 Mhz may be interference with GPS.
Should we go to 8 layers , extra ground planes , spacing and high speed layout.
Grow board in length if we add two connectors?
SDIO and CPU shield ?

Package is $2.67 up to $5 in smaller packages

Debated (cost gradient)
Move to 0201
Microvia’s between pads?
- Goal get two connectors on the board and quiet it down.

• Need PPM pin down to the payload connector 
• Use two connector for debug to allow for trace
	○ One is depop. But needed for trace.

End of summary

Action plan
- Do review of PHY. PHY on Base? Or FMU-M. (USB Phy, ETH Phy)
- Gut feeling is FMU-M will not grow large enough to get PHY’s on there.


S32S - Documentation access soon.
- Block diagram, pincount, peripheral list ,SOM 4-6 weeks.
○ Schematics + 1 month
○ PCB early next year

	○ List of menu of things vs what is possible
		§ 6 SPI
		§ 6UART
		§ 4-8 CAN
		§ 16 
		§ 8 timer in
		§ 4-8 analogs
		§ 8 interrupts
		§ 4-5 I2C (maybe one internal)
	○ NO
		§ FLeXray
		§ Zipwire
		§ SyPhy5 (?)
	○ Peripherals
		§ Gbit phy on SOM
		§ Add RTC
		§ Add Nor Flash
		§ Add ECC 608 key enclave (better supported than internal security module) http://ww1.microchip.com/downloads/en/DeviceDoc/ATECC608A-CryptoAuthentication-Device-Summary-Data-Sheet-DS40001977B.pdf
		§ NXP SBC compliment for power supply of part, with SPI interface
		§ EUI 48 - add a small microchip eeprom with pre-programmed MAC address
			□ Can the SE050 be used to host a preprogrammed MAC address?

From Alex Klimaj to Everyone:  11:23 AM
And the video 
From Jacob Schloss to Everyone:  11:35 AM
24AA025E48T-E/OT for auto temp

• Iain G - action, look at what it would take to do this in the secure element.

Q: Corey - Schedule update on overall milestones
Mechanical geometry?
Ref design published?
A: David S.
Dugan will be +3 week on layout and mechanicals
Realistically - 4 weeks?

It also might be worth considering moving from FRAM to MRAM.


More permanent the Slack document link:

[pixhawk.org] Pixhawk Reference Standard https://docs.google.com/document/d/1KlQeYnhtK43maBSeFuH5s03XsbLIsRVQQ3sZO1HYUM0/edit#heading=h.duvheucksy06

Do you have any cost/size (both physical and capacity) data?

Here are the digikey prices on MRAM.

And here is FRAM. Looks like it is still cheaper to go with FRAM for the same size. But the MRAM is much faster. 40MHz vs 3.4MHz.

Hey guys thanks for posting the notes and links to the docs!

Our team would be a big proponent of implementing the H7 first! The speed and RAM gains over the largest F7s are very attractive and would be a much bigger step up for a relatively minor cost gain and would really help us.

I believe you mentioned during the call that you would post the design files as a snapshot of progress? I would love to take a look. Thanks!